LAN9252SLASHML datasheet(130/329 Pages) MICROCHIP

130 / 329 page

LAN9252

DS00001909A-page 130

 2015 Microchip Technology Inc.

Note 3:

If the mask bit is enabled and the internal interrupt signal has been de-asserted while ENERGYON is still

high, the internal interrupt signal will assert for 256 ms, approximately one second after ENERGYON goes

low when the Cable is unplugged. To prevent an unexpected assertion of the internal interrupt signal, the

ENERGYON interrupt mask should always be cleared as part of the ENERGYON interrupt service routine.

11.2.7.2

Alternate Interrupt Mode

The Alternate interrupt mode is enabled by setting the ALTINT bit of the PHY x Mode Control/Status Register (PHY_-

MODE_CONTROL_STATUS_x) to “1”. In this mode, to enable an interrupt, set the corresponding bit of the in the PHY

x Interrupt Mask Register (PHY_INTERRUPT_MASK_x) (see Table 11-3). To clear an interrupt, clear the interrupt

source and write a ‘1’ to the corresponding Interrupt Source Flag. Writing a ‘1’ to the Interrupt Source Flag will cause

the state machine to check the Interrupt Source to determine if the Interrupt Source Flag should clear or stay as a ‘1’. If

the condition to de-assert is true, then the Interrupt Source Flag is cleared and the internal interrupt signal is also deas-

serted. If the condition to de-assert is false, then the Interrupt Source Flag remains set, and the internal interrupt signal

remains asserted.

Note 4:

LINKSTAT is the internal link status and is not directly available in any register bit.

Note:

The Energy On (ENERGYON) bit in the PHY x Mode Control/Status Register (PHY_MODE_CON-

TROL_STATUS_x) is defaulted to a ‘1’ at the start of the signal acquisition process, therefore the INT7 bit

in the PHY x Interrupt Source Flags Register (PHY_INTERRUPT_SOURCE_x) will also read as a ‘1’ at

power-up. If no signal is present, then both Energy On (ENERGYON) and INT7 will clear within a few mil-

liseconds.

TABLE 11-3:

ALTERNATIVE INTERRUPT MODE MANAGEMENT TABLE

Mask

Interrupt Source Flag

Interrupt Source

Event to

Assert

interrupt

Condition

De-assert

Bit to Clear

interrupt

30.9

29.9

Link Up

LINKSTAT

See

Note 4

Link Status

Rising LINK-

STAT

LINKSTAT

low

29.9

30.8

29.8

Wake on LAN

WOL_INT

See

Note 5

Enabled

WOL event

Rising

WOL_INT

low

29.8

30.7

29.7

ENERGYON

17.1

ENERGYON

Rising 17.1

17.1 low

29.7

30.6

29.6

Auto-Negotia-

tion complete

1.5

Auto-Negoti-

ate Com-

plete

Rising 1.5

1.5 low

29.6

30.5

29.5

Remote Fault

Detected

1.4

Remote

Fault

Rising 1.4

1.4 low

29.5

30.4

29.4

Link Down

1.2

Link Status

Falling 1.2

1.2 high

29.4

30.3

29.3

Auto-Negotia-

tion LP Acknowl-

edge

5.14

Acknowl-

edge

Rising 5.14

5.14 low

29.3

30.2

29.2

Parallel Detec-

tion Fault

6.4

Parallel

Detection

Fault

Rising 6.4

6.4 low

29.2

30.1

29.1

Auto-Negotia-

tion Page

Received

6.1

Page

Received

Rising 6.1

6.1 low

29.1

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