LAN9252SLASHML datasheet(128/329 Pages) MICROCHIP

128 / 329 page

LAN9252

DS00001909A-page 128

 2015 Microchip Technology Inc.

11.2.6

PHY MANAGEMENT CONTROL

The PHY Management Control block is responsible for the management functions of the PHY, including register access

and interrupt generation. A Serial Management Interface (SMI) is used to support registers as required by the IEEE

802.3 (Clause 22), as well as the vendor specific registers allowed by the specification. The SMI interface consists of

the MII Management Data (MDIO) signal and the MII Management Clock (MDC) signal. These signals allow access to

all PHY registers. Refer to Section 11.2.16, "PHY Registers," on page 142 for a list of all supported registers and register

descriptions. Non-supported registers will be read as FFFFh.

11.2.7

PHY INTERRUPTS

The PHY contains the ability to generate various interrupt events. Reading the PHY x Interrupt Source Flags Register

(PHY_INTERRUPT_SOURCE_x) shows the source of the interrupt. The PHY x Interrupt Mask Register (PHY_INTER-

RUPT_MASK_x) enables or disables each PHY interrupt.

The PHY Management Control block aggregates the enabled interrupts status into an internal signal which is sent to

the System Interrupt Controller and is reflected via the PHY A Interrupt Event (PHY_INT_A) and PHY B Interrupt Event

(PHY_INT_B) bits of the Interrupt Status Register (INT_STS). For more information on the device interrupts, refer to

Section 8.0, "System Interrupts," on page 53.

The PHY interrupt system provides two modes, a Primary interrupt mode and an Alternative interrupt mode. Both modes

will assert the internal interrupt signal sent to the System Interrupt Controller when the corresponding mask bit is set.

These modes differ only in how they de-assert the internal interrupt signal. These modes are detailed in the following

subsections.

Note:

When operating in 10BASE-T or 100BASE-TX manual modes, the Auto-MDIX crossover time can be

extended via the Extend Manual 10/100 Auto-MDIX Crossover Time bit of the PHY x EDPD NLP / Cross-

over Time / EEE Configuration Register (PHY_EDPD_CFG_x). Refer to Section 11.2.16.12, on page 159

for additional information.

When Energy Detect Power-Down is enabled, the Auto-MDIX crossover time can be extended via the

EDPD Extend Crossover bit of the PHY x EDPD NLP / Crossover Time / EEE Configuration Register

(PHY_EDPD_CFG_x). Refer to Section 11.2.16.12, on page 159 for additional information

FIGURE 11-4:

DIRECT CABLE CONNECTION VS. CROSS-OVER CABLE CONNECTION

Note:

The Primary interrupt mode is the default interrupt mode after a power-up or hard reset. The Alternative

interrupt mode requires setup after a power-up or hard reset.

TXPx

TXNx

RXPx

Not Used

RXNx

Not Used

TXPx

TXNx

RXPx

Not Used

RXNx

Not Used

Direct Connect Cable

RJ-45 8-pin straight-through

for 10BASE-T/100BASE-TX

signaling

TXPx

TXNx

RXPx

Not Used

RXNx

Not Used

TXPx

TXNx

RXPx

Not Used

RXNx

Not Used

Cross-Over Cable

RJ-45 8-pin cross-over for

10BASE-T/100BASE-TX

signaling

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